How to use the pyboy.core.opcodes_gen.Code function in pyboy

def rotateleft(self, name, left, throughcarry=False):
        code = Code(name, self.opcode, self.name, False, self.length, self.cycles)
        left.assign = False
        if throughcarry:
            code.addline(("t = (%s << 1)" % left.get) + " + cpu.f_c()")
        else:
            code.addline("t = (%s << 1) + (%s >> 7)" % (left.get, left.get))
        code.addlines(self.handleflags8bit(left.get, None, None, throughcarry))
        code.addline("t &= 0xFF")
        left.assign = True
        code.addline(left.set % "t")
        return code

def AND(self):
        if self.name.find(",") > 0:
            r0, r1 = self.name.split()[1].split(",")
            left = Operand(r0)
            right = Operand(r1)
        else:
            r1 = self.name.split()[1]
            left = Operand("A")
            right = Operand(r1)

        code = Code(
            self.name.split()[0], self.opcode, self.name, left.immediate or right.immediate, self.length, self.cycles
        )
        code.addlines(self.ALU(left, right, "&"))
        return code.getcode()

def HALT(self):
        code = Code(self.name.split()[0], self.opcode, self.name, 0, self.length, self.cycles, branch_op=True)

        # TODO: Implement HALT bug. If master interrupt is disabled,
        # the intruction following HALT is skipped
        code.addlines([
            "if cpu.interrupt_master_enable:",
            "\tcpu.halted = True",
            "else:",
            "\tcpu.PC += 1",
            "return " + self.cycles[0],
        ])
        return code.getcode()

def RST(self):
        r1 = self.name.split()[1]
        right = Literal(r1)

        code = Code(self.name.split()[0], self.opcode, self.name, False, self.length, self.cycles, branch_op=True)

        # Taken from PUSH and CALL
        code.addlines([
            "cpu.PC += %s" % self.length,
            "cpu.mb.setitem(cpu.SP-1, cpu.PC >> 8) # High",
            "cpu.mb.setitem(cpu.SP-2, cpu.PC & 0xFF) # Low",
            "cpu.SP -= 2",
        ])

        code.addlines([
            "cpu.PC = %s" % (right.code),
            "return " + self.cycles[0],
        ])

        return code.getcode()

def SBC(self):
        if self.name.find(",") > 0:
            r0, r1 = self.name.split()[1].split(",")
            left = Operand(r0)
            right = Operand(r1)
        else:
            r1 = self.name.split()[1]
            left = Operand("A")
            right = Operand(r1)

        code = Code(
            self.name.split()[0], self.opcode, self.name, left.immediate or right.immediate, self.length, self.cycles
        )
        code.addlines(self.ALU(left, right, "-", carry=True))
        return code.getcode()

def NOP(self):
        code = Code(self.name.split()[0], self.opcode, self.name, 0, self.length, self.cycles)
        return code.getcode()

def XOR(self):
        if self.name.find(",") > 0:
            r0, r1 = self.name.split()[1].split(",")
            left = Operand(r0)
            right = Operand(r1)
        else:
            r1 = self.name.split()[1]
            left = Operand("A")
            right = Operand(r1)

        code = Code(
            self.name.split()[0], self.opcode, self.name, left.immediate or right.immediate, self.length, self.cycles
        )
        code.addlines(self.ALU(left, right, "^"))
        return code.getcode()

left = Operand(r0)
            right = Operand(r1)
        else:
            r1 = self.name.split()[1]
            left = None
            right = Operand(r1)

        if left is not None:
            l_code = left.get
            if l_code.endswith("C") and "NC" not in l_code:
                left.flag = True
                l_code = "cpu.f_c()"
            assert left.flag
        assert right.immediate

        code = Code(
            self.name.split()[0], self.opcode, self.name, right.immediate, self.length, self.cycles, branch_op=True
        )
        if left is None:
            code.addlines([
                "cpu.PC += %d + " % self.length + inline_signed_int8("v"),
                "cpu.PC &= 0xFFFF",
                "return " + self.cycles[0],
            ])
        else:
            code.addlines([
                "cpu.PC += %d" % self.length,
                "if %s:" % l_code,
                "\tcpu.PC += " + inline_signed_int8("v"),
                "\tcpu.PC &= 0xFFFF",
                "\treturn " + self.cycles[0],
                "else:",

def SCF(self):
        code = Code(self.name.split()[0], self.opcode, self.name, False, self.length, self.cycles)
        code.addlines(self.handleflags8bit(None, None, None))
        return code.getcode()